Ingenic Semiconductor

Ingenic Semiconductor is a Chinese fablesssemiconductor company based in Beijing, China founded in 2005. They purchased licenses for the MIPS architectureinstruction sets in 2009 and design CPUmicroarchitectures based on them. They also design system on a chip products including their CPUs and licensed semiconductor intellectual property blocks from third parties, such as Vivante Corporation, commission the fabrication of integrated circuits at semiconductor fabrication plants and sell them.

Ingenic Semiconductor Co., Ltd.
Native name
君正集成电路股份有限公司
Ingenic Semiconductor
Industry Fabless semiconductors, Semiconductors, Integrated circuit design
Founded 2005; 16 years ago (2005)
Founder Liu Qiang (刘强)
Headquarters Beijing, China
Key people
Liu Qiang (Chairman)
Products CPUs (XBurst), SoCs (JZxxx)
Website www.ingenic.com.cn/en

. . . Ingenic Semiconductor . . .

The XBurst CPU microarchitecture is based upon the MIPS32 revision 1 respectively the MIPS32 revision 2 instruction set and implements an 8-stage pipeline. XBurst CPU technology consists of 2 parts:

  • A RISC/SIMD/DSP hybrid instruction set architecture which enables the processor to have the capability of computation, signal processing and video processing. This includes the Media Extension Unit (MXU), a 32-bit SIMD extension. All JZ47xx series CPUs with Xburst uA support MXU, except for the JZ4730.[1][2] MXU has its own register set, distinct from the general purpose MIPS registers. It consists of sixteen 32-bit data registers and a 32-bit control register.[3] CPUs which support MXU are used in MIPS Creator single-board computers. They are also present in various tablets, handheld game devices, and embedded devices.

XBurst2 development was, in summer 2013, expected to be completed by the first half of 2014.[4] However, XBurst2 was eventually introduced in 2020 in the X2000,[5] with the microarchitecture offering a dual-issue/dual-threaded CPU design based on MIPS32 Release 5.[6]

Ingenic JZ4730

SoCs incorporating the XBurst microarchitecture:[7]

Model Launch Fab (nm) XBurst version MIPS architecture version Core clock (MHz) L1 Dcache
[kB]
L1 Icache
[kB]
L2 cache
[kB]
FPU GPU VPU Datasheet Package Notes
Jz4720 2005 180 XBurst1 MIPS32 rev1 240 16 16 N/A N/A N/A N/A Jz4720[permanent dead link]
Jz4725B 2005 160 XBurst1 360 Jz4725
Jz4730 2005 180 XBurst1 336 Jz4730
Jz4740 2007 180 XBurst1 MIPS32 rev1 + SIMD 360 Jz4740 adds RMVB, MPEG-1/2/4 decoding capability up to D-1 resolution thanks to SIMD instruction set
Jz4750 2009 180 XBurst1 MIPS32 rev1 + SIMD2 360 480p Jz4750 adds TV encoder
Jz4755 2009 160 XBurst1 400 576P Jz4755 QFP176 second core is for video processing only
Jz4760 2010 130 XBurst1 600 yes Vivante GC200 720p JZ4760
JZ4760B
BGA345 second core is for video processing only, IEEE754-complient FPU
Jz4770 2011 65 XBurst1 MIPS32 rev2 + SIMD2 1000 256 yes Vivante GC860[8] 1080p JZ4770 BGA379 1080p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)
Jz4775[9] 65 XBurst1 MIPS32 rev2 + SIMD2 1000 32 32 256 yes X2D Core 720p JZ4775 BGA314 720p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)
Jz4780 2012 40 XBurst1 Dual MIPS32 rev2 + SIMD2 1200[10] 32 each 32 each 512 yes PowerVR SGX 540 1080p JZ4780 BGA390 Dual core (SMP) XBurst CPU, 1080p video decoding unit for h.264, VC-1 and VP8 (a secondary 500 MHz MIPS processor with SIMD extension)
x1000[11] 2015[12] 65 XBurst1 MIPS32 + SIMD 1000 16 16 128 yes x1000 BGA190 LPDDR 32/64MB, SLCD interface, Camera interface, Audio Codec up to 192 kHz
x2000 2020[13] 28 XBurst2 Dual MIPS32 + SIMD 1500 32 each 32 each 512 yes 1080p x2000 BGA270 LPDDR2/3 128/256MB

. . . Ingenic Semiconductor . . .

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. . . Ingenic Semiconductor . . .